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14-Bit, 600+ MSPS D/A Converter
Preliminary Technical Data
FEATURES
600+ MSPS DAC update rate 16/14/12/10-bit resolution family LVDS interface with built-in 100-termination resistors Single data rate and double data rate capability Excellent dynamic performance SFDR = 63 dBc at 140 MHz IMD = 73 dBc at 140 MHz Differential current outputs: 2 mA to 20 mA -40C to +85C temperature range operation On-chip 1.20 V reference Package: 80-lead thermally-enhanced TQFP Versatile clock and data interface
AD9725
FUNCTIONAL BLOCK DIAGRAM
CALIBRATION REFERENCE FSADJ REFIO
IOUTA DB[13:0]+ DB[13:0]- DATA FORMATTER DATA SYNC. 14-BIT DAC IOUTB
DDR SDIO DATACLK_IN+ DATACLK_IN- REXT DATACLK_OUT+ DATACLK_OUT- DATA CLOCK FORMATTER CLOCK DISTRIBUTION AND CONTROL SPI SDO/SYNC_ALRM CSB SCLK/SYNC_UPD RESET
APPLICATIONS
Instrumentation and test Wideband communications systems Point-to-point wireless LMDS PA linearization High resolution displays
CLK+ CLK-
04540-0-001
Figure 1
PRODUCT DESCRIPTION
The AD9725 is a 14-bit digital-to-analog converter (DAC) that utilizes an LVDS interface to achieve conversion rates in excess of 600 MSPS. It is in a family of pin compatible converters that offers selection of 10-bit, 12-bit, 14-bit, and 16-bit resolution grades. All of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution and cost.
PRODUCT HIGHLIGHTS
Ultralow noise and intermodulation distortion (IMD) enable high quality waveform synthesis at intermediate frequencies up to 200 MHz. LVDS receivers support SDR or DDR modes, with the maximum conversion rate exceeding 600 MSPS. Manufactured on a CMOS process, the AD9725 uses a proprietary switching technique that enhances dynamic performance. The current output of the AD9725 can be easily configured for various single-ended or differential circuit topologies.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD9725
TABLE OF CONTENTS
Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Digital Timing Information ........................................................ 5 Absolute Maximum Ratings............................................................ 6 Pin Configuration and Function Description .............................. 7 Serial Port Interface Register Maps ................................................ 9 Definitions ....................................................................................... 11 Typical Performance Curves ......................................................... 12 Theory of Operation ...................................................................... 13 LVDS Inputs ................................................................................ 13
Preliminary Technical Data
Data Synchronization Circuitry ............................................... 13 Internal Reference and Full-Scale Output Current................ 13 Analog Output ............................................................................ 14 SPI Port Control ......................................................................... 14 General Operation of the Serial Port Interface ...................... 14 Instruction Byte .......................................................................... 14 Serial Port Interface Pin Description....................................... 14 Notes on Serial Port Operation ................................................ 15 Outline Dimension......................................................................... 16 Ordering Guide .......................................................................... 16
Rev. PrA | Page 2 of 16
Preliminary Technical Data SPECIFICATIONS
DC SPECIFICATIONS
AD9725
Table 1. TMIN to TMAX, AVDD1, AVDD2, DBVDD = 3.3 V, ADVDD, ACVDD, CLKVDD, DVDD = 2.5 V, IOUTFS = 20 mA, unless otherwise noted. Specifications subject to change without notice
Parameter Resolution DC Accuracy Integral Nonlinearity Differential Nonlinearity Analog Output Offset Error Gain Error Full Scale Output Current Output Compliance Range Output Resistance Output Capacitance Reference Output Reference Voltage Reference Output Current Reference Input Reference Input Compliance Range Reference Input Resistance Small Signal Bandwidth Temperature Coefficients Offset Drift Gain Drift (With Internal Reference) Reference Voltage Drift Power Supply1 AVDD1, AVDD2 Voltage Range Analog Supply Current (IAVDD1 + IAVDD2) ADVDD Voltage Range ACVDD Voltage Range Analog Supply Current ( IADVDD + IACVDD) CLKVDD Voltage Range Clock Supply Current (ICLKVDD) DVDD Voltage Range Digital Supply Current (IDVDD) DBVDD Voltage Range Digital Supply Current (IDBVDD) Nominal Power Dissipation (PDIS)2 Nominal Power Dissipation (PDIS)3 Min 14 Typ Max Unit Bits LSB LSB 1 20 1.14 0.1 TBD TBD 1.2 100 1.25 1.26 %FSR %FSR mA V kW pF V nA V kW MHz ppm of FSR/C ppm of FSR/C ppm/C
1.5 0.75 -1
5 0.5 TBD TBD TBD
3.3 51 2.5 2.5 9 2.5 20 2.5 69 3.3 20 479 1000
V mA V mA V mA V mA V mA V mA mW mW
1 2
Supply currents measured under the following conditions: fDAC = 200 MSPS, fOUT = 11 MHz, nominal power supply voltages Power dissipation measured under the following conditions: fDAC = 200 MSPS, fOUT = 11 MHz, nominal power supply voltages 3 Power dissipation measured under the following conditions: fDAC = 600 MSPS, fOUT = 111 MHz, nominal power supply voltages
Rev. PrA | Page 3 of 16
AD9725
AC SPECIFICATIONS
Preliminary Technical Data
Table 2. TMIN to TMAZ, AVDD1, AVDD2, DBVDD = 3.3 V, ADVDD, ACVDD, CLKVDD, DVDD = 2.5 V, IOUTFS = 20 mA, unless otherwise noted. Specifications subject to change without notice.
Parameter Dynamic Performance Max DAC Output Update Rate (DDR) Max DAC Output Update Rate (SDR) AC Linearity Spurious Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS) fDATA = 260 MSPS, fOUT = 20 MHz fDATA = 260 MSPS, fOUT = 70 MHz fDATA = 260 MSPS, fOUT = 120 MHz fDATA = 400 MSPS, fOUT = 20 MHz fDATA = 400 MSPS, fOUT = 70 MHz fDATA = 400 MSPS, fOUT = 140 MHz fDATA = 600 MSPS, fOUT = 20 MHz fDATA = 600 MSPS, fOUT = 125 MHz fDATA = 600 MSPS, fOUT = 250 MHz Two Tone IMD to Nyquist (fOUT1 = fOUT2 = -6 dBFS) fDATA = 300 MSPS, fOUT1 = 26 MHz, fOUT2 = 27 MHz fDATA = 300 MSPS, fOUT1 = 100 MHz, fOUT2 = 101 MHz fDATA = 300 MSPS, fOUT1 = 126 MHz, fOUT2 = 127 MHz fDATA = 500 MSPS, fOUT1 = 26 MHz, fOUT2 = 27 MHz fDATA = 500 MSPS, fOUT1 = 100 MHz, fOUT2 = 101 MHz fDATA = 500 MSPS, fOUT1 = 126 MHz, fOUT2 = 127 MHz fDATA = 600 MSPS, fOUT1 = 26 MHz, fOUT2 = 27 MHz fDATA = 600 MSPS, fOUT1 = 126 MHz, fOUT2 = 127 MHz fDATA = 600 MSPS, fOUT1 = 250 MHz, fOUT2 = 251 MHz Noise Spectral Density (NSD) fDATA = 500 MSPS, fOUT = 20 MHz, 0 dBFS fDATA = 500 MSPS, fOUT = 20 MHz, -12 dBFS fDATA = 500 MSPS, fOUT = 120 MHz, 0 dBFS fDATA = 500 MSPS, fOUT = 120 MHz, -12 dBFS CDMA2000 Adjacent Channel Leakage Ratio (ACLR) fDATA = 245.76 MSPS, IF = 61.44 MHz fDATA = 491.52 MSPS, IF = 122.88 MHz fDATA = 491.52 MSPS, IF = 190 MHz WCDMA Adjacent Channel Leakage Ratio (ACLR), Single Carrier fDATA = 184.32 MSPS, IF = 61.44 MHz fDATA = 245.76 MSPS, IF= 61.44 MHz fDATA = 491.52 MSPS, IF = 122.88 MHz fDATA = 491.52 MSPS, IF = 190 MHz WCDMA Adjacent Channel Leakage Ratio (ACLR), Four Carrier fDATA = 184.32 MSPS, IF = 61.44 MHz, fDATA = 368.64 MSPS, IF = 92.16 MHz Typ 600 440 Unit MSPS MSPS
71 68 68 72 66 60 TBD TBD TBD 89 80 80 90 78 76 TBD TBD TBD -162 -165 -151 -161 TBD TBD TBD 79 79 76 74 69 67
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBc dBc dBc dBc dBc dBc dBc dBc dBc
Rev. PrA | Page 4 of 16
Preliminary Technical Data
DIGITAL SPECIFICATIONS
AD9725
Table 3. TMIN to TMAX, AVDD1, AVDD2, DBVDD = 3.3 V, ADVDD, ACVDD, CLKVDD, DVDD = 2.5 V , IOUTFS = 20 mA, unless otherwise noted. Specifications subject to change without notice.
Parameter Digital Inputs Differential Logic `1' Differential Logic `0' Logic `1' current Logic `0' current Differential Input Resistance Differential Input Capacitance Data Setup Time (tDS) Data Hold Time (tDH) Data Clock Output Delay ( tDCO) Serial Control Bus Maximum SCLK Frequency (fSCLK) Minimum Clock Pulse Width High (tPWH) Minimum Clock Pulse Width Low (tPWL) Maximum Clock Rise/Fall Time Minimum Data/Chip Select Set Up Time (tDS) Minimum Data Hold Time (tDH) Maximum Data Valid Time (tDV) RESET Pulse Width Inputs (SDI, SDIO, SCLK, CSB) Logic `1' Voltage Logic `0' Voltage Logic `1' Current Logic `0' Current Input Capacitance SDIO Output Logic `1' Voltage Logic `0' Voltage Logic `1' Current Logic `0' Current Conditions VCM = 0.875 V to 1.575 V (put into footnote, and delete column?) Min 0.1 -0.6 3.5 3.5 100 3 0.9 -0.3 2.4 15 30 30 1 25 0 30 1.5 2.1 -10 -10 5 DRVDD-0.6 30 30 0.4 50 50 3 0 Typ Max 0.6 -0.1 Unit V V mA mA W pF ns ns ns MHz ns ns ms ns ns ns ns V V A A pF V V mA mA
0.9 +10 +10
DIGITAL TIMING INFORMATION
tDCO
CLK DATACLK_OUT DB[15:0] DATACLK_IN
04540-0-002
tDCO
CLK DATACLK_OUT DB[15:0]
04540-0-003
DATACLK_IN
tDS
tDH
tDS
tDH
tDS
tDH
Figure 2. Single Datarate (SDR) Mode
Figure 3. Double Datarate (DDR) Mode
Rev. PrA | Page 5 of 16
AD9725
ABSOLUTE MAXIMUM RATINGS
Parameter AVDD1, AVDD2, DBVDD ADVDD, ACVDD, CLKVDD, DVDD ACOM1, ACOM2, DBCOM ADCOM, ACCOM, CLKCOM, DCOM REFIO, FSDAJ IOUTA, IOUTB DB0-DB15, DB0-DB15 DATACLKOUT, DATACLKOUT REXT, CLK+, CLKSDO/SYNC_ALRM, SDIO, CSB SCLK/SYNC, RESET DDR, SPI_DIS With Respect to ACOM1, ACOM2, DBCOM ADCOM, ACCOM, CLKCOM, DCOM ACOM1, ACOM2, DBCOM ADCOM, ACCOM, CLKCOM, DCOM ACOM1 ACOM1 DBCOM DBCOM CLKCOM DBCOM DBCOM ADCOM Min -0.3 -0.3 -0.3 -0.3 -0.3 -1 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
Preliminary Technical Data
Max TBD TBD +0.3 +0.3 AVDD1 + 0.3 AVDD1 + 0.3 DBVDD + 0.3 DBVDD + 0.3 CLKVDD + 0.3 DBVDD + 0.3 DBVDD + 0.3 ADVDD + 0.3
Unit V V V V V V V V V V V V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 6 of 16
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTION
SPI_DIS ADVDD ADGND ACVDD ACGND AVDD2 AGND2 AVDD1 AGND1 IOUTA IOUTB AGND1 AVDD1 AGND2 AVDD2 ACGND ACVDD ADGND ADVDD DDR
AD9725
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
CLKVDD REXT CLKVDD CLKGND CLK+ CLK- CLKGND DGND DVDD DB13+ DB13- DB12+ DB12- DB11+ DB11- DB10+ DB10- DB9+ DB9- DBVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60
PIN 1 IDENTIFIER
59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
AD9725
TOP VIEW (Not to Scale)
FSADJ REFIO RESET CSB SCLK/SYNC_UPD SDIO SDO/SYNC_ALRM DGND DVDD NC NC NC NC DB0- DB0+ DB1- DB1+ DB2- DB2+ DBGND
DBGND DB8+ DB8- DB7+ DB7- DB6+ DB6- DATACLK_OUT+ DATACLK_OUT- DBVDD DBGND DATACLK_IN+ DATACLK_IN- DB5+ DB5- DB4+ DB4- DB3+ DB3- DBVDD
Figure 4. Pin Configuration
Table 4. Pin Function Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name CLKVDD REXT CLKVDD CLKGND CLK+ CLK- CLKGND DGND DVDD DB13+ DB13- DB12+ DB12- DB11+ DB11- DB10+ DB10- DB9+ DB9- DBVDD Description Clock Supply Voltage Bias Resistor. Sets DATACLK_OUT drive strength. Nominally 1 k to DBGND Clock Supply Voltage Clock Supply Common Clock Input-True Clock Input-Complement Clock Supply Common Digital Common Digital Supply Voltage Digital Input Bit 13-True Digital Input Bit 13-Complement Digital Input Bit 12-True Digital Input Bit 12-Complement Digital Input Bit 11-True Digital Input Bit 11-Complement Digital Input Bit 10-True Digital Input Bit 10-Complement Digital Input Bit 9-True Digital Input Bit 9-Complement Digital Data Supply Voltage Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name DBGND DB2+ DB2- DB1+ DB1- DB0+ DB0- NC NC NC NC DVDD DGND SDO/SYNC_ALRM SDIO SCLK/SYNC_UPD CSB RESET REFIO FSADJ Description Digital Data Supply Common Digital Input Bit 2-True Digital Input Bit 2-Complement Digital Input Bit 1-True Digital Input Bit 1-Complement Digital Input Bit 0-True Digital Input Bit 0-Complement No Connect No Connect No Connect No Connect Digital Supply Voltage Digital Common SPI_DIS = 1: Data/Clock Synchronization Alarm SPI Serial Data Input/Output SPI_DIS = 1: Data/Clock Synchronization Update Required SPI Chip Select (Active Low) Hardware Reset Reference Output, 1.2 V Nominal Full-Scale Current Adjust
Rev. PrA | Page 7 of 16
04540-0-012
AD9725
Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name DBGND DB8+ DB8- DB7+ DB7- DB6+ DB6- DATACLK_OUT+ DATACLK_OUT- DBVDD DBGND DATACLK_IN+ DATACLK_IN- DB5+ DB5- DB4+ DB4- DB3+ DB3- DBVDD Description Digital Data Supply Common Digital Input Bit 8-True Digital Input Bit 8-Complement Digital Input Bit 7-True Digital Input Bit 7-Complement Digital Input Bit 6-True Digital Input Bit 6-Complement Data Clock Output-True Data Clock Output-Complement Digital Data Supply Voltage Digital Data Supply Common Data Clock Input-True Data Clock Input-Complement Digital Input Bit 5-True Digital Input Bit 5-Complement Digital Input Bit 4-True Digital Input Bit 4-Complement Digital Input Bit 3-True Digital Input Bit 3-Complement Digital Data Supply Voltage Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name DDR ADVDD ADGND ACVDD ACGND AVDD2 AGND2 AVDD1 AGND1 IOUTB IOUTA AGND1 AVDD1 AGND2 AVDD2 ACGND ACVDD ADGND ADVDD SPI_DIS
Preliminary Technical Data
Description SPI_DIS = 1: Double Data Rate Mode (Active High) Analog Supply Voltage Analog Supply Common Analog Supply Voltage Analog Supply Common Analog Supply Voltage Analog Supply Common Analog Supply Voltage Analog Supply Common DAC Current Output-Complement DAC Current Output-True Analog Supply Common Analog Supply Voltage Analog Supply Common Analog Supply Voltage Analog Supply Common Analog Supply Voltage Analog Supply Common Analog Supply Voltage SPI Disable (Active High)
Rev. PrA | Page 8 of 16
Preliminary Technical Data SERIAL PORT INTERFACE REGISTER MAPS
Table 5. Mode Control via SPI Port
Address
COMMS DATA 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11
AD9725
Bit 7
SDIODIR DATAFMT
Bit 6
DATADIR DDR
Bit 5
SWRST DCLKPOLI
Bit 4
SLEEP RESERVED DCLKPOLO RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED CALMEM[0] XFEREN MEMADDR[4] MEMDATA[4]
Bit 3
PDN DISDCLKO
Bit 2
RESERVED1 SYNCMAN
Bit 1
RESERVED SYNCUPD
Bit 0
EXREF SYNCALRM
VERSION CALMEMCK MEMRDWR MEMADDR MEMDATA
RESERVED RESERVED CALSTAT MEMADDR[7] RESERVED
RESERVED RESERVED CALEN MEMADDR[6] RESERVED
RESERVED CALMEM[1] XFERSTAT MEMADDR[5] MEMDATA[5]
VERSION[3] RESERVED SMEMWR MEMADDR[3] MEMDATA[3]
VERSION[2] CALCKDIV[2] SMEMRD MEMADDR[2] MEMDATA[2]
VERSION[1] CALCKDIV[1] FMEMRD MEMADDR[1] MEMDATA[1]
VERSION[0] CALCKDIV[0] UNCAL MEMADDR[0] MEMDATA[0]
1
Reserved registers should be set to Logic 0 (low state) during a write operation, and masked (ignored) during a read operation.
Table 6. SPI Register Definitions
Register COMMCTRL(00) SDIODIR Bit 7 Direction 1 Default 0 Description 0: SDIO pin configured for input only during data transfer 1: SDIO pin configured for input or output during data transfer 0: Serial data uses MSB first format 1: Serial data uses LSB first format 1: Default all serial register bits, except address 00h 1: DAC output current off 1: All analog and digital circuitry, except serial interface, off RESERVED RESERVED 0: Internal bandgap reference 0: Twos complement input data format 1: Unsigned binary input data format 0: Single Data Rate mode 1: Double Data Rate mode 0: Data latched on DATACLKIN rising edge 1: Data latched on DATACLKIN falling edge 0: Data latched on DATACLKOUT rising edge 1: Data latched on DATACLKOUT falling edge 0: DATACLKOUT enabled 1: DATACLKOUT disabled 0: Automatic synchronization initiated following a SYNCALRM 1: Manual synchronization needed following a SYNCALRM
DATADIR SWRST SLEEP PDN RESERVED RESERVED EXREF DATACTRL(02) DATAFMT DDR DCLKPOLI DCLKPOLO DISDCLKO SYNCMAN
6 5 4 3 2 1 0 7 6 5 4 3 2
1 1 1 1 0 0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0
Rev. PrA | Page 9 of 16
AD9725
SYNCUPD SYNCALRM VERSION(0D) VERSION[3:0] CALMEMCK(0E) CALMEM 1 0 1 0 0 0
Preliminary Technical Data
0: Data synchronization complete 1: Initiate data synchronization 0: Data synchronizer does not require updating 1: Data synchronizer requires updating Hardware version identifier Calibration memory 00: Uncalibrated 01: Self calibration 10: Factory calibration 11: User input Calibration clock divide ratio from channel data rate 000:/32 001:/64 110:/2048 111:/4096 0: Self Calibration cycle not complete 1: Self Calibration cycle complete 1: Self Calibration in progress 0: Factory memory transfer not complete 1: Factory memory transfer complete 1: Factory memory transfer in progress 1: Write static memory data from external port 1: Read static memory to external port 1: Read factory memory data to external port 1: Use uncalibrated Address of factory or static memory to be accessed Data for factory or static memory access
[3:0] [5:4]
0 0
- 00
CALCKDIV
[2:0]
1
000
MEMRDWR(0F) CALSTAT CALEN XFERSTAT XFEREN SMEMWR SMEMRD FMEMRD UNCAL MEMADDR(10) MEMADDR MEMDATA(11) MEMDATA
7 6 5 4 3 2 1 0 [7:0] [5:0]
0 1 0 1 1 1 1 1 I/O I/O
0 0 0 0 0 0 0 0 00000000 000000
1: External reference
Rev. PrA | Page 10 of 16
Preliminary Technical Data DEFINITIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero-scale to full-scale.
AD9725
Power Supply Rejection
The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.
Settling Time
The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition.
Differential Nonlinearity ( DNL)
DNL is the measure of the variation in analog value, normalized to full-scale, and associated with a 1 LSB change in digital input code.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s.
Monotonicity
A D/A converter is monotonic if the output either increases or remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s.
Spurious-Free Dynamic Range
The difference, in decibels, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels (dB).
Gain Error
The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s, minus the output when all inputs are set to 0s.
Signal-to-Noise Ratio (SNR)
S/N is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.
Output Compliance Range
The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.
Adjacent Channel Power Ratio (or ACPR)
A ratio in dBc between the measured power within a channel relative to its adjacent channel.
Temperature Drift
Temperature drift is specified as the maximum change from the ambient (25C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree celsius. For reference drift, the drift is reported in ppm per degree celsius.
LVDS
Low voltage differential signaling. A differential logic specification that defines logic levels as approximately 350 mV (differential) over a common mode range of 0.875 V to 1.575 V. LVDS is designed to achieve clock rates of up to 840 MHz.
Rev. PrA | Page 11 of 16
AD9725
TYPICAL PERFORMANCE CURVES
Preliminary Technical Data
Figure 7. Noise Spectral Density vs. fOUT at fDAC = 500 MSPS Figure 5. SFDR vs. fOUT at fDAC = 400 MSPS
Figure 6. IMD vs. fOUT at fDAC = 500 MSPS
Figure 8. WCDMA ACLR at Select Intermediate Frequencies and Sample Rates
Rev. PrA | Page 12 of 16
Preliminary Technical Data THEORY OF OPERATION
LVDS INPUTS
The AD9725 uses LVDS (Low Voltage Differential Signaling) digital inputs to enable high speed digital signaling. LVDS allows the use of a differential signal for optimum noise rejecttion, and has small signal amplitude for fast speed and lower power dissipation. Each differential digital input on the AD9725 has an internal 100 resistor for proper load termination. The LVDS digital data inputs on the AD9725 meet the IEEE reduced range (RR) specs for common mode input range (875 mV to 1575 mV) with an input differential threshold of 350 mV.
AD9725
Once synchronization is established, the AD9725 needs to be reoptimized only if operating conditions change enough to affect the relative phase of the DAC and data clocks by more than one clock cycle. The AD9725 detects when a synchronization update is necessary, and indicates this need by asserting SYNCALRM (02h[0]) or SYNC_ALRM high. If SYNCALRM (02h[0]) or SYNC_ALRM have been asserted, resynchronization can be accomplished as follows: 1. If the synchronization logic is in automatic mode (SYNCMAN (02h[2]) = 0), the synchronization logic will optimize the internal timing as necessary. Two data words will typically be lost or repeated when an optimization occurs. If that possibility could cause serious problems, manual operation may be required. If the synchronization logic is in manual mode (SYNCMAN (02h[2]) = 1), the logic will indicate the need for an update by asserting SYNCALRM (02h[0]) high. In normal operation, a logic high on SYNCALRM (02h[0]) does not mean that data is being lost, but that conditions are close to the point where data may be lost. Optimization should be initiated by setting SYNCUPD (02h[1]) high at a convenient time. Monitoring the synchronization logic state and initiating an update can be done via package pins by setting SPI_DIS high and using the SYNC_ALRM and SYNC_UPD pins in the same way the manual synchronization operation is described in step 2.
DATA SYNCHRONIZATION CIRCUITRY
The high speeds at which the LVDS digital interface is designed to operate require maintaining synchronization of the data (DB[15:0]+, DB[15:0]-) and data clock (DATACLK_IN+, DATACLK_IN-) with the DAC clock (CLK+, CLK-). Since the DAC clock input is not LVDS, the phase relationship between that clock and the data can vary, and, unless precautions are taken, data can be corrupted. The input data must be provided at the same frequency as the DAC clock from an LVDS source with an accompanying LVDS data clock. Since the DAC and data clocks are different types, their phase relationship is difficult to specify. The AD9725 provides internal circuitry to keep the data from being corrupted over a wide variation in relative phase. Once the DAC and data clocks have been established and synchronization has been initiated, the phase between the two clocks can vary by at least one full clock cycle without loss of data. If the phase relationship between the clocks varies enough to cause a possible loss of data, the AD9725 can be resynchronized in several different ways. The internal synchronization circuitry in the AD9725 eases this problem by allowing the phase to vary by at least one full clock cycle, once synchronization has been established. It does this by demultiplexing the incoming data stream into four channels, each containing every fourth data word. Each of these words is present for four DAC clock cycles. The data is then remultiplexed by sampling each channel with the appropriate DAC clock cycle. Initial synchronization is established in one of the following ways: 1. 2. 3. When the RESET pin is asserted, the synchronization logic is initiated to provide optimal internal timing. If SPI_DIS is not asserted, the synchronization is optimized by writing setting SYNC_UPD (02h[1]) high. If SPI_DIS is asserted, the synchronization is optimized by asserting the SYNC_UPD pin. 2.
3.
Note that SYNCUPD (02h[1]) or SYNC_UPD can be asserted at any time to optimize the synchronization, even if SYNCALRM (02h[0]) or SYNC_ALRM have not indicated that it is necessary. If either the data clock or the DAC clock is interrupted for any reason, a SYNCUPD or SYNC_UPD should be executed to insure that no subsequent data is lost.
INTERNAL REFERENCE AND FULL-SCALE OUTPUT CURRENT
The AD9725 contains an internal band gap reference of 1.2 V. The reference voltage is applied to an external resistor at FSADJ, and the resultant current is amplified by the reference buffer to provide the full-scale current for the DAC output. The gain equation from the internal reference to the DAC output (assuming the digital inputs are at full scale) is as follows: IOUTFS = 1.2 x 32/FSADJ Taking into account the state of the digital inputs, the output current of IOUTA and IOUTB at any instant in time is: IOUTA = IOUTFS x (DB15:DB0)/65536 IOUTB = IOUTFS x (1 - DB15:DB0)/65536
Rev. PrA | Page 13 of 16
AD9725
ANALOG OUTPUT
The analog output of the AD9725 is based around a high dynamic range CMOS DAC core. The output consists of a differenttial current source capable of up to 20 mA full-scale. The output devices are PMOS and are capable of sourcing current into an output termination within a compliance voltage range of 1 V. Excellent distortion, noise, and ACLR perfor-mance is achievable to Nyquist at sample rates of 600 MSPS+.
Preliminary Technical Data
INSTRUCTION BYTE
The instruction byte contains the information shown in Table 7 Table 7
N1 0 0 1 1 N0 0 1 0 1 Description Transfer 1 byte Transfer 2 byte Transfer 3 byte Transfer 4 byte
SPI PORT CONTROL
The AD9725 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel SSR protocols. The interface allows read/write access to all registers that configure the AD9725. Single or multiple byte transfers are supported as well as MSB first or LSB first transfer formats. The AD9725 serial interface port can be configured as a single pin I/O (SDIO) or two unidirectional pins for in/out (SDIO/SDO). R/W Bit 7 of the instruction byte determines whether a read or a write data transfer will occur after the instruction byte write. Logic high indicates a read operation. Logic 0 indicates a write operation. N1, N0 -Bits 6 and 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in the following table: Table 8
MSB I7 R/W I6 N1 I5 N0 I4 A4 I3 A3 I2 A2 I1 A1 LSB I0 A0
GENERAL OPERATION OF THE SERIAL PORT INTERFACE
There are two phases to a communication cycle with the AD9725. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9725, and coincident with the first eight SCLK rising edges. The instruction byte provides the AD9725 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines the number of bytes in the data transfer, the starting register address for the first byte of the data transfer, and whether the upcoming data transfer is read or write. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9725. A Logic 1 on the CS pin followed by a Logic 0 will reset the SPI port timing to the initial state of the instruction cycle. This is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the SPI port. If the SPI port is in the midst of an instruction cycle or a data transfer cycle, none of the present data will be written. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9777 and the system controller. Phase 2 of the communication cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. Normally, using one multibyte transfer is the preferred method. However, single byte data transfers are useful to reduce CPU overhead when register access requires 1 byte only. Registers change immediately upon writing to the last bit of each transfer byte.
A4, A3, A2, A1, A0 Bits 4, 3, 2, 1, 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9725.
SERIAL PORT INTERFACE PIN DESCRIPTION
SCLK (Serial Clock)
The serial clock pin is used to synchronize data to and from the AD9725, and to run the internal state machines. The SCLK maximum frequency is 15 MHz. All data input to the AD9725 is registered on the rising edge of SCLK. All data is driven out of the AD9725 on the falling edge of SCLK.
CSB (Chip Select)
Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications line. The SDO and SDIO pins will go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle.
SDIO
Serial data I/O. Data is always written into the AD9725 on this pin. This pin, however, can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of register address 00h. The default is Logic 0, which configures the SDIO pin as unidirectional.
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Preliminary Technical Data
SDO Serial data out. Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9725 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state.
AD9725
NOTES ON SERIAL PORT OPERATION
The AD9725 serial port configuration bits reside in Bit 6 and Bit 7 of register address 00h. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register may occur during the middle of communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle.
INSTRUCTION CYCLE CS
04540-0-009
04540-0-011
04540-0-010
MSB/LSB Transfers
The AD9725 serial port can support both MSB first and LSB first data formats. This functionality is controlled by register address 00h Bit 6. The default is MSB first. When this bit is set to active high, the AD9725 serial port is in LSB first format. That is, if the AD9725 is in LSB first mode, the instruction byte must be written from least significant bit to most significant bit. Multibyte data transfers in MSB format can be completed by writing an instruction byte that includes the register address of the most significant byte. In MSB first mode, the serial port internal byte address generator decrements for each byte required of the multibyte communication cycle. Multibyte data transfers in LSB first format can be completed by writing an instruction byte that includes the register address of the least significant byte. In LSB first mode, the serial port internal byte address generator increments for each byte required of the multibyte communication cycle. The AD9725 serial port controller address will increment from 1Fh to 00h for multibyte I/O operations if the MSB first mode is active. The serial port controller address will decrement from 00h to 1Fh for multibyte I/O operations if the LSB first mode is active.
DATA TRANSFER CYCLE
SCLK SDIO SDO
10 11 12 13 14 15(n) 16(n) R/W D00 D10 D20 D00 D10 D20 D6n D7n D6n D7n
Figure 10. Serial Register Interface Timing LSB First
CS
tDS tPWH
tSCLK tPWL
SCLK
tDS
SDIO
tDH
INSTRUCTION BIT 6
INSTRUCTION BIT 7
Figure 11. Timing Diagram for Register Write to AD9725
CS SCLK
tDV
SDIO SDO DATA BIT n DATA BIT n- 1
Figure 12. Timing Diagram for Register READ to AD9725
INSTRUCTION CYCLE CS SCLK SDIO SDO
R/W 16(n) 15(n) 14 13 12 11 10 D7n D6n D7n D6n D20 D10 D20 D10 D00 D00
DATA TRANSFER CYCLE
The same considerations apply to setting the reset bit in register address 00h. All other registers are set to their default values, but the software reset doesn't affect the bits in register address 00h. It is recommended to use only single byte transfers when changing serial port configurations or initiating a software reset.
Figure 9. Serial Register Interface Timing MSB First
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04540-0-008
AD9725
OUTLINE DIMENSION
0.75 0.60 0.45 SEATING PLANE 1.20 MAX
80 1
Preliminary Technical Data
14.00 SQ 12.00 SQ
61 60 60 61 80 1
PIN 1
TOP VIEW (PINS DOWN)
BOTTOM VIEW
6.00 SQ
20 21 40
41
41 40 21
20
0.15 0.05 1.05 1.00 0.95 0.20 0.09 COPLANARITY 0.08 0.50 BSC 0.27 0.22 0.17
7 3.5 0 GAGE PLANE 0.25
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD
Figure 13. 80-Lead Thin Plastic Quad Flat Package, Exposed Pad [TQFP/ED] (SV-80) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9725BSV Temperature Range -40C to +85C Package Description 80 Lead TQFP Package Option SV-80
THERMAL CHARACTERISTICS Thermal Resistance 80-Lead Thermally Enhanced TQFP Package JA = 23.5C/W* *With thermal pad soldered to PCB.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04682-0-1/04(PrA)
Rev. PrA | Page 16 of 16
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